Integrated circuits (ICs) have numerous interconnecting devices built into a silicon substrate. These devices must be separated, or isolated, to ensure that they function properly, independent of each other. As the need for faster ICs increases, so does the need to be able to place the IC devices closer to each other. As the devices get closer, the need to properly isolate them from each other becomes more critical. To this end, isolation technology has become one of the critical aspects of fabricating ICs.
A conventional process of isolating devices on a flash memory IC is depicted in FIGS. 1A-1B. Referring first to FIG. 1A, the conventional process begins by growing a pad-oxide layer 113 followed by depositing a mask layer 112, such as silicon nitride, which acts as an oxidation barrier layer as well as a polish stop layer on a silicon substrate 110 to form an IC wafer 114. The wafer 114 is divided into two types of regions—array regions where arrays of memory devices will be formed, and periphery regions where the logic devices to control the memory devices will be formed.
A photoresist layer is then formed and patterned to create overlaying photoresist masks 120 on the mask layer 112. As shown in FIG. 1B, trenches 124 are then etched into the silicon substrate 110. Integrated devices can be formed on the raised substrate regions 126 between the trenches 124. The raised substrate regions 126 are known in the art as active regions. Thus, the conventional process uses the same depth trench in both the array and the periphery regions.
A single-depth trench process, however, is sub-optimal for circuits where it may be beneficial to have shallow trenches in the array regions but deeper trenches in the periphery regions. For example, in the array region, smaller trench depths may allow for improved trench fill, preventing voids that result in trenches with a high-aspect ratio. Shallower trench depths may also result in lower resistances in source-rail configurations connecting Flash memory devices, for instance. At the same time, however, trenches may need to be formed in the periphery area that are sufficiently deep to adequately isolate neighboring devices. Hence, an optimized process may include forming shallow trenches and deep trenches on the same substrate.
One process to form shallow trenches in the array regions and deeper trenches in the periphery regions may include steps as shown in FIGS. 1C-1F. Referring first to FIG. 1C, this process may begin by forming a pad-oxide layer 113 on a silicon substrate 110, and a mask layer 112, such as silicon nitride, on the pad-oxide layer 113, to form the IC wafer 114. The wafer 114 is divided into two types of regions—array regions for the formation of memory devices, and periphery regions for the formation of logic devices to control the memory devices. A photoresist layer is then formed and patterned to create overlaying photoresist masks 120 on the mask layer 112. As shown in FIG. 1D, shallow trenches 125 are then etched into the silicon substrate 110 in the array regions.
After stripping the first photo resist mask from the wafer, the optimized process may then continue, as shown in FIG. 1E, with performing a second critical lithography process to pattern photoresist masks 128 on the periphery regions. As ICs get denser with devices, the minimum size features of those devices get smaller and tighter. These minimum size features, or critical dimensions (CD), must be controlled very carefully. To later form devices with the least amount of design error, the photoresist masks 128 on the periphery area would need to be aligned to the array trenches 128 as closely as possible. Therefore, the formation and patterning of the second photoresist layer would require a “critical” lithography process requiring the need for critical steppers. Deep depth trenches 130 would then be etched into the silicon substrate 110 in the periphery, as shown in FIG. 1D. Logic devices could be formed on the raised substrate regions 132 between the deep trenches.
The optimized process, however, also suffers from serious problems. First, because the shallow trenches are formed independently from the deep trenches, the current process requires the use of a second critical lithography process to position the second photoresist masks 128. The second critical lithography process would be required to maintain critical CD control for the periphery area. A critical lithography process requires the use of complex and precise tools that are expensive.
Second no two lithography processes, not even critical lithography processes, can be performed without producing some mis-registration, or overlay error. This mis-registration must be taken into account in the design, thus making the design rules looser, to compensate for the overlay error.
Third, when patterning the deeper trenches 130, the wafer 114 is not planar since the shallow trenches 124 are already formed into the wafer 114. This non-planarity can lead to poor lithography control in the periphery regions.